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\def\webworkCourseName{114\_ELECTRONICS\_2}%
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\def\webworkCourseURL{https://wicswebwork.ee.ncku.edu.tw//webwork2/114\_ELECTRONICS\_2}%
\def\webworkUserId{E24116770}%
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\def\webworkFirstName{蔣智聖}%
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\def\webworkOpenDate{March 19, 2026, 12:01:00 AM CST}%
\def\webworkDueDate{March 26, 2026, 11:59:00 PM CST}%
\def\webworkAnswerDate{March 26, 2026, 11:59:00 PM CST}%

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{\pgmlSetup
This PDF is available for convenience. Assignments must be submitted
within {\bfseries{}WeBWorK} for credit.
\par}%

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\begin{multicols*}{2}
\begin{questions}
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\titledquestion{\ifx\webworkProblemNumber\empty\#\else\webworkProblemNumber\fi}[\ifx\webworkProblemWeight\empty\#\else\webworkProblemWeight\fi]
\smallskip

The MOSFETs in the circuit of Fig. 1 are matched, having
\(k_n'(W/L)_1 = k_p'(W/L)_2 = 1 \, \mathrm{mA/V^2}\) and
\(|V_t| = 0.5 \, \mathrm{V}\). The resistance \(R = 1 \, \mathrm{M\Omega}\).

\leavevmode\\\relax 
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\settoheight{\strutheight}{\strut}\raisebox{-0.5\height + 0.5\strutheight}{\includegraphics[width=0.583\linewidth]{/opt/webwork/courses/114_ELECTRONICS_2/templates/assignment1/problem1_new.png}}


\leavevmode\\\relax 
\leavevmode\\\relax 

(a) For G and D open, what are the drain currents \(I_{D1}\) and \(I_{D2}\)?

\leavevmode\\\relax 
\(I_{D1}\) = {\answerRule[AnSwEr0001]{10}} \(\mathrm{mA}\)

\leavevmode\\\relax 
\(I_{D2}\) = {\answerRule[AnSwEr0002]{10}} \(\mathrm{mA}\)

\leavevmode\\\relax 
\leavevmode\\\relax 

(b) For \(r_o = \infty\), what is the voltage gain of the amplifier from G to D?
(Hint: Replace the transistors with their small-signal models.)

\leavevmode\\\relax 
Voltage gain from G to D = {\answerRule[AnSwEr0003]{10}} \(\mathrm{V/V}\)

\leavevmode\\\relax 
\leavevmode\\\relax 

(c) For finite \(r_o\) (\(|V_A| = 20 \, \mathrm{V}\)), what is the voltage gain from G to D and the input resistance at G?

\leavevmode\\\relax 
Voltage gain from G to D = {\answerRule[AnSwEr0004]{10}} \(\mathrm{V/V}\)

\leavevmode\\\relax 
Input resistance at G = {\answerRule[AnSwEr0005]{10}} \(\mathrm{k\Omega}\)

\leavevmode\\\relax 
\leavevmode\\\relax 

(d) If G is driven (through a large coupling capacitor) from a source \(v_{sig}\) having a resistance of \(20 \, \mathrm{k\Omega}\), find the voltage gain \(v_d/v_{sig}\).

\leavevmode\\\relax 
\(v_d/v_{sig}\) = {\answerRule[AnSwEr0006]{10}} \(\mathrm{V/V}\)

\leavevmode\\\relax 


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\smallskip

A source follower for which \(k_n' = 200 \, \mu A/V^2\),
\(V_A' = 20 \, V/\mu m\), \(\chi = 0.2\), \(L = 0.5 \, \mu m\),
\(W = 20 \, \mu m\), and \(V_t = 0.6 \, V\) is required to provide a dc level
shift (between input and output of \(0.9\,V\).)

What must the bias current be? Find \(g_m\), \(g_{mb}\), \(r_o\), \(A_{vo}\), and \(R_o\).
Assume that the bias current source has an output resistance equal to \(r_o\).
Also find the voltage gain when a load resistance of \(2 \, k\Omega\) is connected to the output.

\leavevmode\\\relax 
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\settoheight{\strutheight}{\strut}\raisebox{-0.5\height + 0.5\strutheight}{\includegraphics[width=0.583\linewidth]{/opt/webwork/courses/114_ELECTRONICS_2/templates/assignment1/problem2_new.png}}


\leavevmode\\\relax 
\leavevmode\\\relax 

Bias current = {\answerRule[AnSwEr0001]{10}} \(mA\)

\leavevmode\\\relax 
\(g_m\) = {\answerRule[AnSwEr0002]{10}} \(mA/V\)

\leavevmode\\\relax 
\(g_{mb}\) = {\answerRule[AnSwEr0003]{10}} \(mA/V\)

\leavevmode\\\relax 
\(r_o\) = {\answerRule[AnSwEr0004]{10}} \(k\Omega\)

\leavevmode\\\relax 
\(A_{vo}\) = {\answerRule[AnSwEr0005]{10}} \(V/V\)

\leavevmode\\\relax 
\(R_o\) = {\answerRule[AnSwEr0006]{10}} \(k\Omega\)

\leavevmode\\\relax 
Voltage gain with \(R_L = 2 \, k\Omega\) : {\answerRule[AnSwEr0007]{10}} \(V/V\)

\leavevmode\\\relax 


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Figure shows a current source realized using a current mirror with two matched transistors \(Q_1\) and \(Q_2\). \leavevmode\\\relax 
Two equal resistances \(R_s\) are inserted in the source leads to increase the output resistance of the current source. \leavevmode\\\relax  
\leavevmode\\\relax 
Given the following parameters: \leavevmode\\\relax 
\(I_{REF} = 110 \mu A\),  \(g_m = 1.7 mA/V\),  \(V_A = 5 V\) \leavevmode\\\relax 
The maximum allowed dc voltage drop across \(R_s\) is \(0.2 V\).
\leavevmode\\\relax 
Assume that the voltage at the common-gate node is approximately constant.
\leavevmode\\\relax 
Find the maximum available output resistance \(R_{out}\) of the current source.
\leavevmode\\\relax 

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 \leavevmode\\\relax 
\(R_{out} =\) {\answerRule[AnSwEr0001]{10}} \(k\Omega\)


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Find the gain \(v_o/i_{sig}\) for the case \leavevmode\\\relax \(g_{m1}  = 3.6\) \(mS\)\leavevmode\\\relax \(g_{m2}  = 4.2\) \(mS\)\leavevmode\\\relax \(\beta_1 = 80.5\)\leavevmode\\\relax \(\beta_2 = 81\)\leavevmode\\\relax \(R_e = 1.9\) \(kΩ\)\leavevmode\\\relax \(R_c = 4\) \(kΩ\)\leavevmode\\\relax \(R_L = 3.7\) \(kΩ\).\leavevmode\\\relax 
(neglect channel-length modulation)
\leavevmode\\\relax \leavevmode\\\relax 
\settoheight{\strutheight}{\strut}\raisebox{-0.5\height + 0.5\strutheight}{\includegraphics[width=0.833\linewidth]{/opt/webwork/courses/114_ELECTRONICS_2/templates/assignment1/problem4.png}}
\leavevmode\\\relax \leavevmode\\\relax 
\leavevmode\\\relax 
  \(v_o/i_{sig}\)= {\answerRule[AnSwEr0001]{10}}\(\) \(Ω\)\leavevmode\\\relax  \leavevmode\\\relax  







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 \leavevmode\\\relax  \leavevmode\\\relax 

A CMOS cascode amplifier is shown in the figure above. Both transistors \(Q_1\) and \(Q_2\) are identical and are biased at a DC current \(I = 0.15 \text{ mA}\). 
\leavevmode\\\relax 
The given parameters for the ideal calculations are:
\leavevmode\\\relax 
\(\mu_n C_{ox} = 400 \ \mu\text{A/V}^2\)
\leavevmode\\\relax 
\(W/L = 5.4 \mu\text{m} / 0.36 \mu\text{m}\)
\leavevmode\\\relax 
\(V_A' = 5 \text{ V}/\mu\text{m}\)
\leavevmode\\\relax  \leavevmode\\\relax 

\par\hrulefill\par 
{\bf  Part 1: Theoretical Calculation } \leavevmode\\\relax 
Calculate the required load resistor \(R_L\) so that the overall voltage gain \(A_v = \frac{v_o}{v_i}\) is exactly \(-104 \text{ V/V}\). What is the voltage gain of the common-source stage (the \(Q_1\) stage)?
\leavevmode\\\relax 
(\(R_o\) & \(R_{in2}\) is used the approximate formula to calculate and Assume the transistors are operating in the saturation region).
\leavevmode\\\relax  \leavevmode\\\relax 
\(R_L =\) {\answerRule[AnSwEr0001]{7.5}} \(\text{k}\Omega\)
\leavevmode\\\relax  \leavevmode\\\relax 
\(A_{v1} =\) {\answerRule[AnSwEr0002]{10}} \(\text{V/V}\)
\leavevmode\\\relax  

\par\hrulefill\par 
{\bf  Part 2: PSpice Simulation Assignment } \leavevmode\\\relax 
In this part, you will verify the circuit using a real device model in PSpice. 
Due to the nonlinear characteristics of real transistors, the simulated gain will differ from your ideal calculation.
\leavevmode\\\relax  \leavevmode\\\relax 
{\bf  Instructions:}
\leavevmode\\\relax 
1. Build the circuit in PSpice using the \(\text{NMOS0P18}\) provided in moodle for both \(Q_1\) and \(Q_2\).
\leavevmode\\\relax 
2. Use an ideal DC voltage source  to provide the VDD voltage \(V = 3.3 \text{ V}\), gate voltage of Q1 is \(Vdc = 0.6 \text{ V}\) & \(Vac = 1 \text{ V}\),gate voltage of Q2 is \(Vdc = 1.5 \text{ V}\)
\leavevmode\\\relax 
3. Set the resistor \(R_L\) to the exact value you calculated in Part 1
\leavevmode\\\relax 

4. Perform an AC Sweep simulation.
\leavevmode\\\relax 
5. Measure the  voltage gain \(\frac{v_{o}}{v_i}\) &  \(\frac{v_{o1}}{v_i}\)
\leavevmode\\\relax  \leavevmode\\\relax 

{\bf  Submission:} \leavevmode\\\relax 
Please take screenshots of:
\leavevmode\\\relax 
- Your PSpice schematic .
\leavevmode\\\relax 
- The AC sweep plot showing the gain \(\frac{v_{o}}{v_i}\) &  \(\frac{v_{o1}}{v_i}\) .
\leavevmode\\\relax 


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